1. Field of the Invention
The invention relates to data transfers over busses, and more specifically to systems which can change the data width used in transferring the data.
2. Description of the Related Art
Data transfers between input/output (I/O) devices in computers and memory in the computers are always desired to be as fast as possible. To this end direct memory access (DMA) controllers have been developed so that these transfers can take place without placing a large burden on the system processor.
These transfers take place over a bussing arrangement at predefined speeds. For example, in the International Business Machines Corp. (IBM) PC, 20 bits of address, eight bits of data and a basic timing cycle of approximately 1 microsecond per cycle (for an 8 MHZ bus clock rate) were used in DMA transfers. This data transfer rate was improved in the IBM PC/AT by the use of a 16 bit data transfer. However, this still left the fastest basic rate available at 2 Mbytes per second which became slow as the speed of the various I/O devices increased and the processors became wider and faster.
To help resolve this problem the Extended Industry Standard Architecture (EISA) was developed. The EISA specification Version 3.1 is provided as Exhibit A in U.S. Pat. No. 5,101,492, filed Sep. 3, 1989, issued Mar. 31, 1992, and entitled Data Redundancy and Recovery Protection, and is incorporated by reference in its entirety. The EISA specification defines several very high speed DMA transfer options referred to as burst transfers. These transfers allow data to be transferred every BCLK signal cycle, with the BCLK signal being the basic synchronizing signal of the bus. The transfers can be either 16 or 32 bits wide for burst transfers, but if the responding memory device does not have a width consistent with the I/O device or the memory device it cannot burst, and then the transfer rate is reduced. In the cases of mismatched data width, the rate drops appreciably because the bus controller must perform assembly/disassembly cycles as defined by the EISA specification, which slow down each transfer. If the memory device is the same width but does not support the burst function, the transfer rate is reduced, but only to that of the basic, default timing, which is not as appreciable a drop as in the mismatched cases. Thus, while it is desirable to use burst modes, the communicating devices must be of compatible widths or the advantage will be lost.
Conventionally two methods were used to buffer data between the memory and the I/O device. The first method was used with small buffers, while the second method was used with larger buffers. When only the smaller buffers are needed, a first in first out (FIFO) circuit was used. This FIFO consisted of a series of stacked data registers which passed data from one register to another as the data exited or entered the FIFO. Typical FIFO devices were 8 bits wide and 64 positions deep. For a 32 bit buffer four of such devices were required if the depth was sufficient. However, these FIFO devices were uni-directional, which means that data enters in one side and exits the other, so that an additional set of devices was necessary to handle data flow in the opposite direction. Alternatively, rerouting logic was developed to route logic through the same chips but then bi-directional, interleaved operation was lost.
For larger buffers of the second method a FIFO random access memory (RAM) controller (FRC) device was used. This FRC device was used in conjunction with conventional static random access memory (SRAM) devices. The FRC device provided a larger FIFO by using each SRAM location as a register. The SRAM address was controlled from within the FRC device so that rather than passing data from one register to another, an address pointer was incremented. Internal counters in the FRC device incremented with each cycle in the transfer. A single FRC chip could control any single data width since it only generated addresses. However, the FRC device is unidirectional and so external logic or two devices were needed to provide by-directional capability.
Problems did arise when multiple widths of information had to be passed using an FRC device. If the FRC device was configured such that the SRAM's were designed to be 32 bits wide, data transfers occurred optimally for 32 bit transfers. However, if 16 bit data had to be transferred using this 32 bit configuration, data was not transferred into 16 bits of the SRAM and so the effective buffer space was reduced to one-half the total supplied space. Alternatively, the SRAM's could be configured for 16 bit operation, but then the FRC device would not properly increment addresses for 32 bit operation. Therefore the FRC device could only work for fixed data widths, unless buffer size reduction was acceptable.